branch target buffer

基本解釋

The fetcher also generates a search address for output to the branch target buffer.
指令讀取器亦產生搜尋位址輸出至分支目標緩沖器中。
The branch target buffer is provided with a tag RAM that is organized in a set associative fashion.
分支目標緩沖器提供一個架構成集合相關式的標簽…
Using system simulator, we synthetized the effect of the prediction scheme and the branch target buffer. The conclusion is useful to the single-issue-pipeline microprocessor design.
實驗基于系統(tǒng)級模擬器，綜合轉移預測策略和轉移目標緩沖器行為進行完整模擬，結論對于其它采用單發(fā)射流水線結構的微處理器設計具有較好的借鑒意義。