bus latency

基本解釋

Thus, it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate.
因此研究系統(tǒng)總線協(xié)議及其實(shí)現(xiàn)技術(shù)對(duì)于隱藏訪存延遲和提高訪存速度具有重要意義。
Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.
片外存儲(chǔ)系統(tǒng)的訪存延遲主要由DRAM延遲決定，帶寬則是由內(nèi)存總線的數(shù)據(jù)傳輸率所決定。
The recent Standards & Specs article on bus architectures discusses some of the issues; raw bandwidth and latency are two of the major influences on how much it matters.
有關(guān)總線架構(gòu)的最近標(biāo)準(zhǔn)規(guī)范文章討論了這方面的一些問題；原始帶寬和延時(shí)是影響它的兩個(gè)主要因素。

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