combinational logic circuit

基本解釋

And combinational logic circuits by using VHDL language and in two ways, comparing the merits of the two implementations and different design processes and ideas.
并且通過(guò)應(yīng)用組合邏輯電路和VHDL語(yǔ)言實(shí)現(xiàn)兩種方法，對(duì)照了兩種實(shí)現(xiàn)方法的優(yōu)劣及不同的設(shè)計(jì)流程和思想。
The properties of Boolean difference are made use of to derive a new method for fault testing in combinational logic circuits. This method is simpler and different from the traditional one.
本文利用布爾差分的性質(zhì)，給出了一種不同于傳統(tǒng)的求組合邏輯線路故障測(cè)試碼的新方法，對(duì)故障測(cè)試有一定的簡(jiǎn)化作用。
The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance.
仿真實(shí)驗(yàn)結(jié)果證明了改進(jìn)演化算法對(duì)于實(shí)現(xiàn)函數(shù)級(jí)數(shù)字組合邏輯電路的硬件演化是可行的，并且提高了演化算法的演化效率和收斂性能。