digital adder

基本解釋

Addend and the summand input, and digital and carry the output device is a half adder.
加法器是産生數(shù)的和的裝置。加數(shù)和被加數(shù)爲輸入，和數(shù)與進位爲輸出的裝置爲半加器。
A digital adder needs more circuitry, and thus more power, to operate, but it does not require such high accuracy.
數(shù)字加法器需要更多的電路、因而需要更大的功率才能工作，但它不需要這麼高的準確性。
We take the Full Adder as an example to introduce the use of VHDL in the design of digital system, the experiment of digital circuit and the teaching.
本文以全加器爲例介紹其在數(shù)字系統(tǒng)設計和數(shù)字電路實騐及教學中的應用。