sampling hold circuit

基本解釋

Sampling rate and holding accuracy are two most concerned targets in designing the sample-and-hold circuit.
採(cǎi)樣速度和保持精度，是採(cǎi)樣保持電路設(shè)計(jì)制作者最爲(wèi)關(guān)注的兩項(xiàng)指標(biāo)。
The signal accepted by ultrasonic probe passes disposing circuit, magnifying, sieving its waves, passing demodulation, sampling and holding system and then comes into A/D conversion.
信號(hào)由接收探頭傳到信號(hào)処理電路，經(jīng)過放大、濾波、檢波、採(cǎi)樣保持進(jìn)入A／D轉(zhuǎn)換器。
The circuit is divided into full bridge module, charge sense amplifier module, correlated double sampling and holding module, closed-loop feedback module, low-pass filter and time controlling module.
檢測(cè)電路分爲(wèi)全橋平衡模塊、電荷放大器模塊、信號(hào)放大模塊、相關(guān)雙採(cǎi)樣模塊、採(cǎi)樣保持模塊、閉環(huán)反餽模塊、低通濾波模塊和數(shù)字時(shí)序控制模塊。