signal dispose

基本解釋

The schemes to dispose of reset signal and clock signal in VHDL high-level synthesis are given also.
還給出了高級綜郃中複位信號和時(shí)鍾信號的処理方法。
The hardware of the system is composed of three parts: dispose the analog signal to be in the right range;
撥道系統(tǒng)的硬件部分爲(wèi)三個(gè)部分：對輸入的模擬信號進(jìn)行処理使信號的範(fàn)圍達(dá)到要求；
At first the filter based on mathematical morphology is applied to dispose the disturbance signal in advance. A multiple structuring element complex filter is created to restrain many kinds of noise.
首先利用數(shù)學(xué)形態(tài)學(xué)對擾動波形進(jìn)行預(yù)処理，再使用分形技術(shù)檢測電能質(zhì)量擾動，最後用模式識別確定擾動類型。

信號処理
Hardware system use TI company's DSP chip TMS320LF2407A for core. Because of DSP chip have quickly signal dispose speed,so insure system high detect precision.
其中硬件系統(tǒng)以TI公司的DSP芯片TMS320LF2407A爲(wèi)核心,由於DSP芯片的信號処理速度快,確保了本系統(tǒng)的高測量精度。