clock-tree

基本解釋

It reduces switched capacitance by turning off transitions on a clock tree when the triggered registers do not need to change their values.
當(dāng)暫存器內(nèi)儲(chǔ)存的值不需要改變時(shí)，可以藉著關(guān)閉時(shí)脈訊號(hào)的切換來(lái)降低切換電容的值。
First, we propose a topology generation method to generate the clock tree topology with minimal output net loading.
首先，我們提出一個(gè)時(shí)鐘樹(shù)拓樸生成方法來(lái)產(chǎn)生擁有最小輸出負(fù)載的時(shí)鐘樹(shù)拓樸。
It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits.
PP-流水線還可以降低流水線電路的時(shí)鐘樹(shù)功耗。
Besides, bounded-skew clock tree is proposed to shorten the total wirelength of a clock net, implying lower power dissipation.
除此之外，利用限制時(shí)序差異的時(shí)鐘樹(shù)可以縮短時(shí)脈訊號(hào)的線路長(zhǎng)度，這也暗示了可以達(dá)到更低的功率消耗。
Among clock network designs, the buffered clock tree architecture is the most popular clock network design adopted in modern VLSI designs.
在時(shí)鐘網(wǎng)路的設(shè)計(jì)中，目前最普遍采用在現(xiàn)今晶片設(shè)計(jì)的是緩沖器式時(shí)鐘樹(shù)。