clock-tree

基本解釋

It reduces switched capacitance by turning off transitions on a clock tree when the triggered registers do not need to change their values.
儅暫存器內(nèi)儲存的值不需要改變時，可以藉著關(guān)閉時脈訊號的切換來降低切換電容的值。
First, we propose a topology generation method to generate the clock tree topology with minimal output net loading.
首先，我們提出一個時鍾樹拓樸生成方法來産生擁有最小輸出負(fù)載的時鍾樹拓樸。
It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits.
PP-流水線還可以降低流水線電路的時鍾樹功耗。
Besides, bounded-skew clock tree is proposed to shorten the total wirelength of a clock net, implying lower power dissipation.
除此之外，利用限制時序差異的時鍾樹可以縮短時脈訊號的線路長度，這也暗示了可以達到更低的功率消耗。
Among clock network designs, the buffered clock tree architecture is the most popular clock network design adopted in modern VLSI designs.
在時鍾網(wǎng)路的設(shè)計中，目前最普遍採用在現(xiàn)今晶片設(shè)計的是緩沖器式時鍾樹。